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publication number s29gl-p_00 revision a amendment 3 issue date november 21, 2006 s29gl-p mirrorbit tm flash family s29gl-p mirrorbit tm flash family cover sheet s29gl01gp, s29gl512p, s29gl256p, s29gl128p 1 gigabit, 512 megabit , 2 56 megabit an d 128 megabit 3.0 volt-only page mode flash memory featuring 90 nm mirrorbit process technology data sheet (advance information) notice to readers: this document contains information on o ne or more products under development at spansion inc. the information is intended to help yo u evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice.
ii s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document contains information on one or more products under development at spansion inc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed pr oduct without notice. publication number s29gl-p_00 revision a amendment 3 issue date november 21, 2006 general description the spansion s29gl01g/512/256/128p are mirro rbit? flash products fabricated on 90 nm process technology. these devices offer a fast page access time of 25 ns with a corres ponding random access time of 110 ns. they feature a write buffer that allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. this makes these device s ideal for today?s embedded applic ations that require higher density, better performance and lower power consumption. distinctive characteristics ? single 3v read/program/erase (2.7-3.6 v) ? enhanced versatilei/o? control ? all input levels (address, control, and dq input levels) and outputs are determined by voltage on v io input. v io range is 1.65 to v cc ? 90 nm mirrorbit process technology ? 8-word/16-byte page read buffer ? 32-word/64-byte write buffer reduces overall programming time for multiple-word updates ? secured silicon sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number ? can be programmed and locked at the factory or by the customer ? uniform 64kword/128kbyte sector architecture ? s29gl01gp: one thousand twenty-four sectors ? s29gl512p: five hundred twelve sectors ? s29gl256p: two hundred fifty-six sectors ? s29gl128p: one hundred twenty-eight sectors ? 100,000 erase cycles per sector typical ? 20-year data retention typical ? offered packages ? 56-pin tsop ? 64-ball fortified bga ? suspend and resume commands for program and erase operations ? write operation status bits indicate program and erase operation completion ? unlock bypass program command to reduce programming time ? support for cfi (common flash interface) ? persistent and password methods of advanced sector protection ? wp#/acc input ? accelerates programming time (when v acc is applied) for greater throughput during system production ? protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion performance characteristics * access times are dependent on v cc and v io operating ranges. see ordering information page for further details. v1: v cc = 3.0?3.6 v. v2: v cc = v io = 2.7?3.6 v. v3: v io = 1.65?v cc , v cc = 3 v. ** contact a sales representative for availability. s29gl-p mirrorbit tm flash family s29gl01gp, s29gl512p, s29gl256p, s29gl128p 1 gigabit, 512 megabit , 2 56 megabit an d 128 megabit 3.0 volt-only page mode flash memory featuring 90 nm mirrorbit process technology data sheet (advance information) max. read access times (ns)* parameter 512/256/128 mb** 1 gb v1 v2 v3 v1 v2 v3 random access time (t acc ) 100 110 120 110 120 130 page access time (t pac c ) 252525252525 ce# access time (t ce ) 110 110 120 110 120 130 oe# access time (t oe ) 252530252530 current consumption (typical values) random access read 30 ma 8-word page read 1 ma program/erase 50 ma standby 1 a program & erase times (typical values) single word programming 60 s effective write buffer programming (v cc ) per word 15 s effective write buffer programming (v acc ) per word 15 s sector erase time (64 kword sector) 0.5 s
2 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) table of contents general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 recommended combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. input/output descrip tions & logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. physical dimensions/connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 special handling instructions for bga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 laa064?64 ball fortified ball grid array, 11 x 13 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 ts056?56-pin standard thin small outline package (t sop) . . . . . . . . . . . . . . . . . . . . . . 11 5. additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 specification bulletins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 hardware and software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 5.4 contacting spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 word/byte configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 versatileio tm (v io ) control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 page read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.8 write operation status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.9 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8. advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2 persistent protection bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.3 persistent protection bit lock bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.4 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.5 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.6 hardware data protection methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9. power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3 hardware reset# inpu t operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10. secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.1 factory locked secured siliconsector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2 customer lockable secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.3 secured silicon sector en try/exit command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 3 data sheet (advance information) 11.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.3 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.4 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.5 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.7 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12. appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.1 command definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.2 common flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13. revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 list of figures figure 3.1 s29gl-p block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4.1 64-ball fortified ball grid array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4.2 laa064?64ball fortified ball grid array (fbga), 11 x 13 mm . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4.3 56-pin thin small outline package (tsop), 14 x 20 mm . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6.1 s29gl01gp sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7.1 single word program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7.2 write buffer programming operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 7.3 sector erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7.4 write operation status flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 8.1 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 8.2 ppb program/erase algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 8.3 lock register program algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 11.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 11.2 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 11.3 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 11.4 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 11.5 read operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 11.6 page read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 11.7 reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 11.8 power-up sequence timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 11.9 program operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 11.10 accelerated program timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 11.11 chip/sector erase operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 11.12 data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 11.13 toggle bit timings (during embe dded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 11.14 dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 11.15 alternate ce# controlled write (erase/program) operation timings . . . . . . . . . . . . . . . . . . 59 list of tables table 2.1 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 6.1 s29gl512p sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6.2 s29gl256p sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6.3 s29gl128p sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 7.1 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 7.2 autoselect codes, (high voltage method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7.3 autoselect addresses in system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 7.4 autoselect entry in system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 7.5 autoselect exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) table 7.6 single word/byte program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7.7 write buffer program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 7.8 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 7.9 chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 7.10 erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 7.11 erase resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 7.12 program suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 7.13 program resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 7.14 unlock bypass entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 7.15 unlock bypass program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 7.16 unlock bypass reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 7.17 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 7.18 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 8.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 8.2 sector protection schemes: dyb, ppb and ppb lo ck bit combinations . . . . . . . . . . . . . . .43 table 10.1 secured silicon sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 10.2 secured silicon sector entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 10.3 secured silicon sector program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 10.4 secured silicon sector exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 11.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 11.2 s29gl-p dc characteristics (cmos compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 11.3 s29gl-p read-only operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 11.4 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 11.5 power-up sequence timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 11.6 s29gl-p erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 11.7 s29gl-p alternate ce# contro lled erase and program operations . . . . . . . . . . . . . . . . . . .58 table 11.8 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 12.1 s29gl-p memory array command definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 12.2 s29gl-p sector protection comm and definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 12.3 s29gl-p memory array command definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 12.4 s29gl-p sector protection comm and definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 12.5 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 12.6 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 12.7 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 12.8 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 5 data sheet (advance information) 1. ordering information the ordering part number is formed by a valid combination of the following: notes 1. type 0 is standard. specify other options as required. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading ?s29? and packing type designator from ordering part number. 4. contact local sales representative for availability, and on the following part numbers: s29gl01gp12tfi010, s29gl01gp12ffi010, s29gl01gp13tfiv10, s29gl01gp13ffiv10. 1.1 recommended combinations recommended combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific recommended combinations and to check on newly released combinations. s29gl01gp s29gl512p s29gl256p s29gl128p 10 f a i 01 0 packing type 0 = tray (standard; see (note 1) 2 = 7? tape and reel 3 = 13? tape and reel model number (v io range, protection when wp# =v il ) 01 = v io = v cc = 2.7 to 3.6 v, highest address sector protected 02 = v io = v cc = 2.7 to 3.6 v, lowest address sector protected v1 = v io = 1.65 to v cc , v cc = 2.7 to 3.6 v, highest address sector protected v2 = v io = 1.65 to v cc , v cc = 2.7 to 3.6 v, lowest address sector protected r1 = v io = v cc = 3.0 to 3.6 v, highest address sector protected r2 = v io = v cc = 3.0 to 3.6 v, lowest address sector protected temperature range i = industrial (?40c to +85c) package materials set a= pb (note 4) f = pb-free package type t = thin small outline package (tsop) standard pinout f = fortified ball grid array, 1.0 mm pitch package speed option 11 = 110 ns 12 = 120 ns 13 = 130 ns device number/description s29gl01gp, s29gl512p, s29gl256p, s29gl128p 3.0 volt-only, 1024, 512, 256 and 128 megabit (32 m x 16-bit/64 m x 8-bit) page-mode flash memory manufactured on 90 nm mirrorbit tm process technology s29gl-p valid combinations package description 1gb speed (ns) package & temperature model number pack type s29gl01gp 11 tai , tfi (note 4) r1, r2 0, 3 (note 1) ts056 (tsop) (note 2) 12 01 (note 4) , 02 13 v1 (note 4) , v2 11 fai , ffi (note 4) r1, r2 0, 2, 3 (note 1) laa064 (fortified bga) (note 3) 12 01 (note 4) , 02 13 v1 (note 4) , v2 s29gl512p, s29gl256p, s29gl128p (note 4)
6 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 2. input/output descriptions & logic symbol table 2.1 identifies the input and output packa ge connections provided on the device. table 2.1 input/output descriptions symbol type description a25?a0 input address lines for gl01gp a24?a0 for gl512p a23?a0 for gl256p, a22?a0 for gl128p. dq14?dq0 i/o data input/output. dq15 i/o dq15: data input/output in word mode . a-1: lsb address input in byte mode. ce# input chip enable. oe# input output enable. we# input write enable. v cc supply device power supply. v io supply versatile io input. v ss supply ground. nc no connect not connected internally. ry/by# output ready/busy. indicates whether an embedded algorit hm is in progress or complete. at v il , the device is actively erasing or progra mming. at high z, the device is in ready. byte# input selects data bus width. at v il , the device is in byte configuration and data i/o pins dq0- dq7 are active. at v ih , the device is in word config uration and data i/o pins dq0-dq15 are active. reset# input hardware reset. low = device resets and returns to reading array data. wp#/acc input write protect/acceleration input. at v il , disables program and erase functions in the outermost sectors. at v hh , accelerates programming; automatically places device in unlock bypass mode. should be at v ih for all other conditions. rfu reserved reserved for future use.
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 7 data sheet (advance information) 3. block diagram figure 3.1 s29gl-p block diagram 4. physical dimensions/connection diagrams this section shows the i/o designations and package specifications for the s29gl-p. 4.1 related documents the following documents contain information relating to the s29gl-p devices. click on the title or go to www.spansion.com download the pdf file, or request a copy from your sales office. ? considerations for x-ray inspection of su rface-mounted flash integrated circuits 4.2 special handling instructions for bga package special handling is required for flash memory products in bga packages. flash memory devices in bga packages may be damage d if exposed to ultrasonic cleaning m ethods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150c for prolonged periods of time. input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# wp#/acc byte# ce# oe# stb stb dq15 ? dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a max **?a0 ** a max gl01gp=a25, a max gl512p = a24, a max gl256p = a23, a max gl128p = a22
8 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) figure 4.1 64-ball fortified ball grid array a2 c2 d2 e2 f2 g2 h2 a 3 c 3 d 3 e 3 f 3 g 3 h 3 a4 c4 d4 e4 f4 g4 h4 a5 c5 d5 e5 f5 g5 h5 a6 c6 d6 e6 f6 g6 h6 a7 c7 d7 e7 f7 g7 h7 dq15/a-1 v ss byte# a16 a15 a14 a12 a1 3 dq1 3 dq6 dq14 dq7 a11 a10 a 8 a9 v cc dq4 dq12 dq5 a19 a21 re s et# we# dq11 dq 3 dq10 dq2 a20 a1 8 wp#/acc ry/by# dq9 dq1 dq 8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a 3 a1 c1 d1 e1 f1 g1 h1 rfu rfu v io rfu rfu rfu rfu rfu a 8 c 8 b2 b 3 b4 b5 b6 b7 b1 b 8 d 8 e 8 f 8 g 8 h 8 a25 rfu a24 v ss v io a2 3 a22 rfu rfu on s 29gl12 8 p rfu on s 29gl256p rfu on s 29gl512p do not connect to v ss . 64-ball fortified bga top view, balls facing down
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 9 data sheet (advance information) 4.3 laa064?64 ball fortified ball grid array, 11 x 13 mm figure 4.2 laa064?64ball fortified ball grid array (fbga), 11 x 13 mm
10 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 a2 3 a22 a15 a14 a1 3 a12 a11 a10 a9 a 8 a19 a20 we# re s et# a21 wp#/acc ry/by# a1 8 a17 a7 a6 a5 56 55 54 5 3 52 51 50 49 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 a24 a25 a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq1 3 dq5 dq12 dq4 v cc dq11 dq 3 dq10 dq2 dq9 dq1 dq 8 dq0 2 3 24 25 26 27 2 8 a4 a 3 a2 a1 rfu rfu 3 4 33 3 2 3 1 3 0 29 oe# v ss ce# a0 rfu v io do not connect to v ss . nc on s 29gl512p nc on s 29gl256p nc on s 29gl12 8 p 56-pin standard tsop (top view)
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 11 data sheet (advance information) 4.4 ts056?56-pin standard thin small outline package (tsop) figure 4.3 56-pin thin small outline package (tsop), 14 x 20 mm notes: 1 controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982.) 2 pin 1 identifier for standard pin out (die up). 3 to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 4 dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15 mm per side. 5 dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 mm total in excess of b dimension at max material condition. minimum space between protrusion and an adjacent lead to be 0.07 mm. 6 these dimesions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 7 lead coplanarity shall be within 0.10 mm as measured from the seating plane. 8 dimension "e" is measured at the centerline of the leads. 3160\38.10a mo-142 (b) ec ts 56 nom. --- --- 1.00 1.20 0.15 1.05 max. --- min. 0.95 0.20 0.23 0.17 0.22 0.27 0.17 --- 0.16 0.10 --- 0.21 0.10 20.00 20.20 19.80 14.00 14.10 13.90 0.60 0.70 0.50 -8? 0? --- 0.20 0.08 56 18.40 18.50 18.30 0.05 0.50 basic e r b1 jedec package symbol a a2 a1 d1 d c1 c b e l n o
12 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 5. additional resources visit www.spansion.com to obtain the following related documents: 5.1 application notes the following is a list of application notes related to this product. all spansion application notes are available at http://www.spansion.com/support/techni cal_documents/application_notes.html ? using the operation status bits in amd devices ? understanding page mode flash memory devices ? mirrorbit? flash memory write buffer programming and page buffer read ? common flash interface version 1.4 vendor specific extensions 5.2 specification bulletins contact your local sales office for details. 5.3 hardware and software support downloads and related information on flash device support is available at www.spansion.com/support/index.html ? spansion low-level drivers ? enhanced flash drivers ? flash file system downloads and related information on simulation modeling and cad modeling support is available at http:// www.spansion.com/support/simulation_models.html ? vhdl and verilog ? ibis ? orcad an faq (frequently asked questions) list is available at www.spansion.com/support/ses/index.html 5.4 contacting spansion obtain the latest list of company locations and contact information on our web site at www.spansion.com/about/location.html
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 13 data sheet (advance information) 6. product overview the s29gl-p family consists of 1 gb, 512 mb, 256 mb and 128 mb, 3.0-volt-onl y, page mode flash devices optimized for today?s embedded designs that demand a large storage array and rich functionality. these devices are manufactured using 90 nm mirrorbit techno logy. these products offer uniform 64 kword (128 kb) uniform sectors and feature versatileio control, allowing control and i/o si gnals to operate from 1.65 v to v cc . additional features include: ? single word programming or a 32-word buffer for an increased programming speed ? program suspend/resume and erase suspend/resume ? advanced sector protection methods for protecting sectors as required ? 128 words of secured silicon area for storing cust omer and factory secured information. the secured silicon sector is one time programmable. 6.1 memory map the s29gl-p devices consist of uniform 64 kw ord (128 kb) sectors organized as shown in table 6.1 ? table 6.4 . note this table has been condensed to show sector-related information for an entire device on a single page. sectors and their addre ss ranges that are not explicitly listed (such as sa001-sa1022) have sector starting and ending addresses that form the same pattern as a ll other sectors of that size. for example, all 128 kb sectors have the pattern xxx0000h-xxxffffh. note this table has been condensed to show sector-related information for an entire device on a single page. sectors and their addre ss ranges that are not explicitly listed (such as sa001-sa510) have sector starting and ending addresses thatthe same pattern as all othe r sectors of that size. for example, all 128 kb se ctors have the pattern xxx0000h-xxxffffh. note this table has been condensed to show sector-related information for an entire device on a single page. sectors and their addre ss ranges that are not explicitly listed (such as sa001-sa254) have sector starting and ending addresses that form the same pattern as al l other sectors of that size. for example, all 128 kb sectors have the pattern xxx0000h-xxxffffh. table 6.1 s29gl01gp sector & memory address map uniform sector size sector count sector range address range (16-bit) notes 64 kword/128 kb 1024 sa00 0000000h - 000ffffh sector starting address : : sa1023 3ff0000h - 3ffffffh sector ending address table 6.2 s29gl512p sector & memory address map uniform sector size sector count sector range address range (16-bit) notes 64 kword/128 kb 512 sa00 0000000h - 000ffffh sector starting address : : sa511 1ff0000h - 1ffffffh sector ending address table 6.3 s29gl256p sector & memory address map uniform sector size sector count sector range address range (16-bit) notes 64 kword/128 kb 256 sa00 0000000h - 000ffffh sector starting address : : sa255 0ff0000h - 0ffffffh sector ending address
14 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) note this table has been condensed to show sector-related information for an entire device on a single page. sectors and their addre ss ranges that are not explicitly listed (such as sa001-sa510) have sector starting and ending addresses that form the same pattern as al l other sectors of that size. for example, all 128 kb sectors have the pattern xxx0000h-xxxffffh. 7. device operations this section describes the read, program, erase, ha ndshaking, and reset features of the flash devices. operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see table 12.1 through table 12.4 ). the command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute t he command. the contents of the register serve as input to the internal state machine and the state machi ne outputs dictate the functi on of the device. writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode. 7.1 device operation table the device must be setup appro priately for each operation. table 7.1 describes the required state of each control pin for any particular operation. legend l = logic low = v il , h = logic high = v ih , v hh = 11.5?12.5v, x = don?t care, a in = address in, d in = data in, d out = data out notes 1. addresses are amax:a0 in word mode; a max :a-1 in byte mode. 2. if wp# = v il , on the outermost sector remains protected. if wp# = v ih , the outermost sector is unprotected. all sectors are unprotected when shipped from the factory (the secured silicon sector can be factory protected depending on version ordered.) 3. d in or d out as required by command sequence, data polling, or sector protect algorithm. table 6.4 s29gl128p sector & memory address map uniform sector size sector count sector range address range (16-bit) notes 64 kword/128 kb 128 sa00 0000000h - 000ffffh sector starting address : : sa127 07f0000 - 7fffff sector ending address table 7.1 device operations operation ce# oe# we# reset# wp#/acc addresses (note 1) dq0?dq7 dq8?dq15 byte#= v ih byte#= v il read l l h h x a in d out d out dq8?dq14 = high-z, dq15 = a-1 write (program/erase) l h l h (note 2) a in (note 3) (note 3) accelerated program l h l h v hh a in (note 3) (note 3) standby v cc 0.3 v x x v cc 0.3 v h x high-z high-z high-z output disable l h h h x x high-z high-z high-z reset x x x l x x high-z high-z high-z
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 15 data sheet (advance information) 7.2 word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or wo rd configuration. if the byte# pin is set at logic ?1?, the device is in word con-figuration, dq0-dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq0-dq7 are active and controlled by ce# and oe#. the data i/o pi ns dq8-dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. 7.3 versatileio tm (v io ) control the versatileio tm (v io ) control allows the host system to set the voltage levels that the device generates and tolerates on ce# and dq i/os to the sa me voltage level that is asserted on v io . see ordering information for v io options on this device. for example, a v io of 1.65-3.6 volts allows for i/o at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 v devices on the same data bus. 7.4 read all memories require access time to output array data. in a read operation, data is read from one memory location at a time. addresses are presented to the de vice in random order, and the propagation delay through the device causes the data on its outputs to arrive with the address on its inputs. the device defaults to reading array data after device power-up or hardware re-set. to read data from the memory array, the system must firs t assert a valid address on amax-a0, while driving oe# and ce# to v il . we# must remain at v ih . all addresses are latched on the falling edge of ce#. data will appear on dq15- dq0 after ad-dress access time (t acc ), which is equal to the delay from stable addresses to valid output data. the oe# signal must be driven to v il . data is output on dq15-dq0 pins after the access time (t oe ) has elapsed from the falling edge of oe#. 7.5 page read mode the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 8 words/16 bytes. the appropriate page is selected by the higher address bits a(max)-a3. address bits a2-a0 in word mode (a2-a-1 in byte mode) determine the specific word within a page. the microprocessor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor fa lls within that page) is equivalent to t pac c . when ce# is de- asserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode accesses are obtained by keeping the ?read-page addresses? constant and changing the ?intra-read page? addresses.
16 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 7.6 autoselect the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output from the internal register (separate from the memory array) on dq7-dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm (see table 7.3 ). the autoselect code s can also be accessed in-system. when verifying sector protection, the sector address must appear on the appropria te highest order address bits (see table 7.4 to table 7.5 ). the remaining address bits are don't care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15- dq0. the autoselect codes can also be acce ssed in-system through the command register. there are two methods to access autoselect codes. one uses the autoselect co mmand, the other applies v id on address pin a9. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins must be as shown in table 7.2 . ? to access the autoselect codes, the host system must issue the autoselect command. ? the autoselect command sequence may be written to an add ress within a sector that is either in the read or erase-suspend-read mode. ? the autoselect command may not be written while the device is actively programming or erasing. ? the system must write the reset command to return to the read mode (or erase-suspend-read mode if the sector was previously in erase suspend). ? see table 12.1 on page 61 for command sequence details.
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 17 data sheet (advance information) legend l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. v id = 11.5v to 12.5v table 7.2 autoselect codes, (high voltage method) description ce# oe# we# amax to a16 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 byte# = v ih byte# = v il manufacturer id : spansion product llh x xv id xlxlll 00 x 01h device id s29gl01gp cycle 1 llh x xv id xlx llh 22 x 7eh cycle 2 h h l 22 x 28h cycle 3 h h h 22 x 01h device id s29gl512p cycle 1 llh x xv id xlx llh 22 x 7eh cycle 2 h h l 22 x 23h cycle 3 h h h 22 x 01h device id s29gl256p cycle 1 llh x xv id xlx llh 22 x 7eh cycle 2 h h l 22 x 22h cycle 3 h h h 22 x 01h device id s29gl128p cycle 1 llh x xv id xlx llh 22 x 7eh cycle 2 h h l 22 x 21h cycle 3 h h h 22 x 01h sector group protection verification llhsaxv id xlxlhl x x 01h (protected), 00h (unprotected) secured silicon sector indicator bit (dq7), wp# protects highest address sector llh x xv id xlxlhh x x 99h (factory locked), 19h (not factory locked) secured silicon sector indicator bit (dq7), wp# protects lowest address sector llh x xv id xlxlhh x x 89h (factory locked), 09h (not factory locked) table 7.3 autoselect addresses in system description address read data (word/byte mode) manufacturer id (base) + 00h xx01h/1h device id, word 1 (base) + 01h 227eh/7eh device id, word 2 (base) + 0eh 2228h/28h (gl01gp) 2223h/23h (gl512p) 2222h/22h (gl256p) 2221h/21h (gl128p) device id, word 3 (base) + 0fh 2201h/01h secure device verify (base) + 03h for s29glxxxph: xx19h/19h = not factory locked. xx99h/99h = factory locked. for s29glxxxpl: xx09h/09h = not factory locked. xx89h/89h = factory locked. sector protect verify (sa) + 02h xx01h/01h = locked, xx00h/00h = unlocked
18 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) software functions and sample code note 1. any offset within the device works. 2. base = base address. the following is a c source code example of using the autoselect function to read the manufacturer id. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (uint16 *)base_addr + 0x000 ); /* read manuf. id */ /* autoselect exit */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* exit autoselect (write reset command) */ table 7.4 autoselect entry in system (lld function = lld_autoselectentrycmd) cycle operation byte address word address data unlock cycle 1 write basexaaah basex555h 0x00aah unlock cycle 2 write basex555h basex2aah 0x0055h autoselect command write basexaaah basex555h 0x0090h table 7.5 autoselect exit (lld function = lld_autoselectexitcmd) cycle operation byte address word address data unlock cycle 1 write base + xxxh base + xxxh 0x00f0h
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 19 data sheet (advance information) 7.7 program/erase operations these devices are capable of several modes of progra mming and or erase operations which are described in detail in the following sections. during a write operation, the system must drive ce# and we# to v il and oe# to vih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. the unlock bypass feature allows the host system to send program commands to the flash device without first writing unlock cycles within the command sequence. see section 7.7.8 for details on the unlock bypass function. note the following: ? when the embedded program algorithm is complete, the device returns to the read mode. ? the system can determine the status of the program operation by using dq7 or dq6. refer to the write operation stat section for information on these status bits. ? an ?0? cannot be programmed back to a ?1.? a succeeding read shows that the data is still ?0.? ? only erase operations can convert a ?0? to a ?1.? ? any commands written to the device during the embedded program algorithm are ignored except the program suspend command. ? secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. ? a hardware reset immediately terminates the program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? programming is allowed in any sequence and across sector boundaries for single word programming operation. ? programming to the same word address multiple times without intervening erases is permitted. 7.7.1 single word programming single word programming mode is one method of programming the flash. in this mode, four flash command write cycles are used to program an individual flash addr ess. the data for this programming operation could be 8 or 16-bits wide. while the single word programming method is support ed by all spansion devices, in general it is not recommended for devices that suppor t write buffer programming. see table 12.1 on page 61 for the required bus cycles and figure 7.1 for the flowchart. when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the prog ram operation by using dq7 or dq6. refer to the write operation status section for in formation on these status bits. ? during programming, any command (except t he suspend program command) is ignored. ? the secured silicon sector, autoselect, and cfi functi ons are unavailable when a program operation is in progress. ? a hardware reset immediately terminates the progra m operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? programming to the same address multiple times continuo usly (for example, ?walking? a bit within a word) is permitted.
20 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) figure 7.1 single word program write unlock cycle s : addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h write progr a m comm a nd: addre ss 555h, d a t a a0h progr a m d a t a to addre ss : pa , p d unlock cycle 1 unlock cycle 2 s et u p comm a nd progr a m addre ss (pa), progr a m d a t a (pd) fail. i ssu e re s et comm a nd to ret u rn to re a d a rr a y mode. perform polling algorithm ( s ee write oper a tion s t a t us flowch a rt) ye s ye s no no polling s t a t us = b us y? polling s t a t us = done? error condition (exceeded timing limit s ) pa ss . device i s in re a d mode.
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 21 data sheet (advance information) software functions and sample code note base = base address. the following is a c source code example of using the single word program function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: program command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll for program completion */ 7.7.2 write buffer programming write buffer programming allows the system to write a maximum of 32 wo rds in one programming operation. this results in a faster effective word programming time than the standard ?word? programming algorithms. the write buffer programming comma nd sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle cont aining the write buffer load command written at the sector address in which programming occurs. at this point, the system writ es the number of ?word locations minus 1? that are loaded into the page buffer at the sector address in which programming occurs. this tells the device how many write buffer addresses are loa ded with data and therefore when to ex pect the ?program buffer to flash? confirm command. the number of lo cations to program cannot exceed th e size of the write buffer or the operation aborts. (number loaded = the number of locations to program minus 1. for example, if the system programs 6 address locations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starti ng address is the first address/data pair to be programmed, and selects the ?write-buffer-pag e? address. all subsequent address/data pairs must fall within the elect ed-write-buffer-page. the ?write-buffer-page? is selected by using the addresses a max ?a5. the ?write-buffer-page? addresses must be the same fo r all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performe d across multiple ?write- buffer-pages.? this also means that write buffer programming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected ?write-buffer-page?, the operation aborts.) after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. note that if a write buffer address location is l oaded multiple times, the ?address/data pair? counter is decremented for every data load operation. also, the last data loaded at a location before the ?program buffer to flash? confirm command is programmed into the device. it is the software's responsibility to comprehend ramifications of loading a write-buffer location mo re than once. the counter decrements for each data load operation, not for each unique write-buffer-address lo cation. once the specified number of write buffer locations have been loa ded, the system must then writ e the ?program buffer to fl ash? command at the sector address. any other address/data wr ite combinations abort the write buffer programming operation. the device goes ?busy.? the data bar polling techniques should be used while monitoring the last address location loaded into the write buffer. this eliminat es the need to store an address in memory because the system can load the last address location, issue th e program confirm command at the last lo aded address location, and then data bar poll at that same address. dq7, dq6, dq5, dq2, and dq1 should be monitored to determine the device status dur ing write buffer programming. table 7.6 single word/byte program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 555h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write byte address word address data
22 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) the write-buffer ?embedded? progra mming operation can be suspended using the standard suspend/resume commands. upon successful completion of the write buff er programming operation, the device returns to read mode. the write buffer programming sequence is abor ted under any of the following conditions: ? load a value that is greater than the page buffer size during the ?number of locations to program? step. ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different write-buffe r-page than the one selected by the ?starting address? during the ?write buffer data loading? stage of the operation. ? write data other than the ?confirm command? after the specified number of ?data load? cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the ?last address location loaded?), dq6 = toggle, dq5 = 0. this indicates that the write bu ffer programming operation was aborted. a ?write-to- buffer-abort reset? command sequence is required wh en using the write buffer programming features in unlock bypass mode. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. write buffer programming is allowed in any sequence of memory (or address) locations. these flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. use of the write buffer is strongly recommende d for programming when multiple words are to be programmed.
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 23 data sheet (advance information) software functions and sample code notes 1. base = base address. 2. last = last cycle of write buffer program operation; depend ing on number of words written, the total number of cycles may be from 6 to 37. 3. for maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (n words) possible . the following is a c source code example of using the write buffer program function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (uint16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (uint16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *( (uint16 *)addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)addr + 0x555 ) = 0x00f0; /* write buffer abort reset */ table 7.7 write buffer program (lld functions used = lld_writetobuf fercmd, lld_programbuffertoflashcmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 555h base + 2aah 0055h 3 write buffer load command write sector address 0025h 4 write word count write secto r address word count (n?1)h number of words (n) loaded into the write buffer can be from 1 to 32 words (1 to 64 bytes). 5 to 36 load buffer word n write program address, word n word n last write buffer to flash write sector address 0029h
24 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) figure 7.2 write buffer programming operation write unlock cycle s : addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h i ssu e write b u ffer lo a d comm a nd: addre ss s a, d a t a 25h lo a d word co u nt to progr a m progr a m d a t a to addre ss : s a, wc unlock cycle 1 unlock cycle 2 wc = n u m b er of word s ? 1 ye s ye s ye s ye s ye s no no no no no wc = 0? write b u ffer a b ort de s ired? write b u ffer a b ort? polling s t a t us = done? error? fail. i ssu e re s et comm a nd to ret u rn to re a d a rr a y mode. write to a different s ector addre ss to c aus e write b u ffer a b ort pa ss . device i s in re a d mode. confirm comm a nd: s a = 0x29h w a it 4 m s (recommended) perform polling algorithm ( s ee write oper a tion s t a t us flowch a rt) write next word, decrement wc: wc = wc ? 1 re s et. i ssu e write b u ffer a b ort re s et comm a nd
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 25 data sheet (advance information) 7.7.3 sector erase the sector erase function erases one or more sectors in the memory array. (see table 12.1 on page 61 and figure 7.3 .) the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire me mory for an all zero data pattern prior to electrical erase. after a successful sect or erase, all locations with in the erased sector cont ain ffffh. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than 50 s occurs. during the time- out period, additional sector addresse s and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of se ctors may be from one sector to all sectors. the time between these additional cycl es must be less than 50 s. any sector erase add ress and command following the exceeded time-out (50s) may or may not be accepted. any command ot her than sector erase or erase suspend during the time-out period resets that sector to t he read mode. the system can monitor dq3 to determine if the sector erase timer has timed out (see section 7.8.6 .) the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the sect or returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7 or dq6/dq2 in the erasing sector. refer to section 7.8 for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset imme diately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiat ed once that sector has returned to reading array data, to ensure the sector is properly erased. the unlock bypass feature allows the host system to send program commands to the flash device without first writing unlock cycles within the command sequence. see section 7.7.8 for details on the unlock bypass function. figure 7.3 illustrates the algorithm for the erase operation. refer to section 11.7.5 for parameters and timing diagrams. software functions and sample code the following is a c source code example of us ing the sector erase function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: sector erase command * / *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0030; /* write sector erase command */ table 7.8 sector erase (lld function = lld_sectorerasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 555h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 555h base + 2aah 0055h 6 sector erase command write sec tor address sector address 0030h unlimited additional sectors may be selected for erase; command(s) must be written within 50 s.
26 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) figure 7.3 sector erase operation notes 1. see table 12.1 on page 61 for erase command sequence. 2. see the section on dq3 for information on the sector erase timeout. no write unlock cycle s : addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h write s ector er as e cycle s : addre ss 555h, d a t a 8 0h addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h s ector addre ss , d a t a 3 0h write addition a l s ector addre ss e s fail. write re s et comm a nd to ret u rn to re a ding a rr a y. pa ss . device ret u rn s to re a ding a rr a y. w a it 4 m s (recommended) perform write oper a tion s t a t us algorithm s elect addition a l s ector s ? unlock cycle 1 unlock cycle 2 ye s ye s ye s ye s ye s no no no no l as t s ector s elected? done? dq5 = 1? comm a nd cycle 1 comm a nd cycle 2 comm a nd cycle 3 s pecify fir s t s ector for er asu re error condition (exceeded timing limit s ) s t a t us m a y b e o b t a ined b y re a ding dq7, dq6 a nd/or dq2. poll dq 3 . dq 3 = 1? ? e a ch a ddition a l cycle m us t b e written within t s ea timeo u t ? the ho s t s y s tem m a y monitor dq 3 or w a it t s ea to en su re a ccept a nce of er as e comm a nd s ? no limit on n u m b er of s ector s ? comm a nd s other th a n er as e sus pend or s electing a ddition a l s ector s for er asu re d u ring timeo u t re s et device to re a ding a rr a y d a t a (see figure 7.4 )
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 27 data sheet (advance information) 7.7.4 chip erase command sequence chip erase is a six-bus cycle operation as indicated by table 12.1 on page 61 . these commands invoke the embedded erase algorithm, which does not require the system to preprog ram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. after a successful chip erase, all lo cations of the chip contain ffffh. the system is not required to provide any controls or timings during thes e operations. the ?command definition? section in the appendix shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that sector returns to the read mode and addresses are no longer latched. the system ca n determine the status of the erase operation by usi ng dq7 or dq6/dq2. refer to ?write operation status? for information on these status bits. the unlock bypass feature allows the host system to send program commands to the flash device without first writing unlock cycles within the command sequence. see section 7.7.8 for details on the unlock bypass function. any commands written during the chip erase operati on are ignored. however, note that a hardware reset immediately terminates the erase operation. if that o ccurs, the chip erase command sequence should be reinitiated once that sector has returned to reading array data, to ensure the entire array is properly erased. software functions and sample code the following is a c source code example of us ing the chip erase function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: chip erase command */ /* note: cannot be suspended */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */ table 7.9 chip erase (lld function = lld_chiperasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 555h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 555h base + 2aah 0055h 6 chip erase command write base + aaah base + 555h 0010h
28 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 7.7.5 erase suspend/erase resume commands the erase suspend command allows the system to inte rrupt a sector erase operation and then read data from, or program data to, any sector not selected for er asure. the sector address is required when writing this command. this command is valid only during the sector erase operation, including the minimum 50 s time- out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 20 s (5 s typical) to suspend the erase oper ation. however, when the erase suspend command is written during the sector erase time-out, th e device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-suspen d-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any addre ss within erase-suspended se ctors produces status information on dq7-dq0. th e system can use dq7, or dq6, and dq2 t ogether, to determine if a sector is actively erasing or is erase-suspended. refer to table 7.35 for information on these status bits. after an erase-suspended program operation is comple te, the device returns to the erase-suspend-read mode. the system can determine the st atus of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. in the erase-susp end-read mode, t he system can also issue the autosele ct command sequenc e. refer to the ?write buffer programming operation? section and th e ?autoselect command sequence? section for details. to resume the sector erase operat ion, the system must write the er ase resume command. the address of the erase-suspended sector is required when writing th is command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. software functions and sample code the following is a c source code example of us ing the erase suspend function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: erase suspend command */ *( (uint16 *)base_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of us ing the erase resume function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: erase resume command */ *( (uint16 *)sector_addr + 0x000 ) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ table 7.10 erase suspend (lld function = lld_erasesuspendcmd) cycle operation byte address word address data 1 write base + xxxh base + xxxh 00b0h table 7.11 erase resume (lld function = lld_eraseresumecmd) cycle operation byte address word address data 1 write sector address sector address 0030h
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 29 data sheet (advance information) 7.7.6 program suspend/p rogram resume commands the program suspend command allows the system to interrupt an embedded programming operation or a ?write to buffer? programming operation so that data can read from any non-suspended sector. when the program suspend command is written during a progra mming process, the device halts the programming operation within 15 s maximum (5 s typical) and updates the status bi ts. addresses are ?don't-cares? when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non- suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area, then us er must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in program suspend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the auto select mode, the device reverts to program suspend mode, and is ready for another valid operation. s ee ?autoselect command sequence? for more information. after the program resume command is written, th e device reverts to prog ramming. the system can determine the status of the program operation using the dq7 or dq6 stat us bits, just as in the standard program operation. see ?write oper ation status? for more information. the system must write the program resume command (address bits are ?don't care?) to exit the program suspend mode and continue the programming operation. further writes of the program resume command are ignored. another program suspend command can be written after the device has resumed programming. software functions and sample code the following is a c source code example of usin g the program suspend function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: program suspend command */ *( (uint16 *)base_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of usi ng the program resume function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: program resume command */ *( (uint16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ table 7.12 program suspend (lld function = lld_programsuspendcmd) cycle operation word address data 1 write base + xxxh 00b0h table 7.13 program resume (lld function = lld_programresumecmd) cycle operation word address data 1 write base + xxxh 0030h
30 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 7.7.7 accelerated program accelerated single word programming and write buffe r programming operations are enabled through the wp#/acc pin. this method is faster t han the standard program command sequences. note the accelerated program functions must not be used more than 10 times per sector. if the system asserts v hh on this input, the device automatica lly enters the aforementioned unlock bypass mode and uses the higher voltage on the input to redu ce the time required for program operations. the system can then use the write buffer load command se quence provided by the unlock bypass mode. note that if a ?write-to-buffer-abort reset? is requir ed while in unlock bypass mode, the full 3-cycle reset command sequence must be used to reset the device. removing v hh from the acc input, upon completion of the embedded program operation, returns the device to normal operation. ? sectors must be unlocked prior to raising wp#/acc to v hh . ? the wp#/acc pin must not be at v hh for operations other than accele rated programming, or device damage may result. ? the wp#/acc pin must not be left floating or unconnect ed; inconsistent behavior of the device may result. 7.7.8 unlock bypass the device features an unlock bypass mode to facilitate faster word programming. once the device enters the unlock bypass mode, only two write cycles are r equired to program data, in stead of the normal four cycles. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. the ?command definition summary? section shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode , the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the sector address and the data 90h. the second cycle need only contain the data 00h. the sector then returns to the read mode. software functions and sample code the following are c source code examples of using t he unlock bypass entry, program, and exit functions. refer to the spansion low level driver user?s guide (available soon on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: unlock bypass entry command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ table 7.14 unlock bypass entry (lld function = lld_unlockbypassentrycmd) cycle description operation word address data 1 unlock write base + 555h 00aah 2 unlock write base + 2aah 0055h 3 entry command write base + 555h 0020h
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 31 data sheet (advance information) /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *( (uint16 *)base_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; 7.8 write operation status the device provides several bits to determine the st atus of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. 7.8.1 dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the co mmand sequence. note that the data# polling is valid only for the last word being programmed in the writ e-buffer-page during write buffer programming. reading data# polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that sector returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the er ase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprote cted sectors, and ignores the selected sectors that are protecte d. however, if the system reads dq 7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded progra m or erase operation, dq 7 may change with dq6-dq0 while output enable (oe#) is asserted low. that is, the device may change from pr oviding status information table 7.15 unlock bypass program (lld function = lld_unlockbypassprogramcmd) cycle description operation word address data 1 program setup command write base +xxxh 00a0h 2 program command write program address program data table 7.16 unlock bypass reset (lld function = lld_unlockbypassresetcmd) cycle description operation word address data 1 reset cycle 1 write base +xxxh 0090h 2 reset cycle 2 write base +xxxh 0000h
32 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6-dq0 may be still invalid. valid data on dq7-d00 appears on successive read cycles. see the following for more information: table 7.17 , shows the outputs for data# polling on dq7. figure 7.4 , shows the data# polling algorithm; and figure 11.7 , shows the data# polling timing diagram. figure 7.4 write operation status flowchart start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read1 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 ? valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error program operation complete read3= valid data? yes no notes: 1) dq6 is toggling if read2 dq6 does not equal read3 dq6. 2) dq2 is toggling if read2 dq2 does not equal read3 dq2. 3) may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4) write buffer error if dq1 of last read =1. 5) invalid state, use reset command to exit operation. 6) valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) data polling algorithm valid for all operations except advanced sector protection. device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5)
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 33 data sheet (advance information) 7.8.2 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the se ctor erase time-out. during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if no t all selected sectors are protected, the embedded erase algorithm erases the unprotected sect ors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protec ted sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for additional information: figure 7.4 , figure 11.13 on page 57 , and table 7.17 . toggle bit i on dq6 requires either oe# or ce# to be de-asserted and reasserted to show the change in state. 7.8.3 dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is actively erasing or is erase- suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bi ts are required for sector and mode information. refer to table 7.17 to compare outputs for dq2 and dq6. see figure 11.14 on page 57 for additional information. 7.8.4 reading toggle bits dq6/dq2 whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, th e system would note and store the value of the toggle bit after the first read. after the second read, th e system would compare the new value of the toggle bit with the first. if the toggle bit is no t toggling, the device has completed the program or erases operation. the system can read array data on dq7? dq0 on the follo wing read cycle. however, if after the in itial two read cycles, the system determines that the toggle bit is st ill toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stoppe d toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has succes sfully completed the program or er ases operation. if it is still toggling, the device did not complete the operati on successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. th e system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choo se to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to det ermine the status of the operation. refer to figure 7.4 for more details. note when verifying the status of a writ e operation (embedded program/erase) of a memory sector, dq6 and dq2 toggle between high and low states in a series of consec utive and con-tiguous status read cycles. in order for
34 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) this toggling behavior to be properly observed, the cons ecutive status bit reads must not be interleaved with read accesses to other memory sectors. if it is not possible to temporarily prevent reads to other memory sectors, then it is recommended to use the dq7 status bit as the alternative method of determining the active or inactive status of the write operation. 7.8.5 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the system must write the reset command to return to the read mode (or to the erase-suspend- read mode if a sector was previously in the erase-suspend-program mode). 7.8.6 dq3: sector erase timeout state indicator after writing a sector erase comm and sequence, the system may read dq 3 to determ ine whether or not erasure has begun. (the sector erase ti mer does not apply to the chip eras e command.) if additional sectors are selected for erasure, the entire time-out also ap plies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0 ? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, then the system need not monitor dq3. see sector erase command sequence for more details. after the sector erase command is wr itten, the system should re ad the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (e xcept erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device accepts additional sector erase commands. to ensure the command has been accepted, the system softwa re should check the status of dq3 prior to and following each sub-sequent sector erase command. if dq 3 is high on the second status check, the last command might not have been accepted. table 7.17 shows the status of dq3 relative to the other status bits. 7.8.7 dq1: write to buffer abort dq1 indicates whether a write to buffer operation was aborted. under these condit ions dq1 produces a ?1?. the system must issue the write to buffer abort rese t command sequence to return the device to reading array data. see write buffer program ming operation for more details.
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 35 data sheet (advance information) notes 1. dq5 switches to 1 when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to 1 when the device has aborted the write-to-buffer operation 7.9 writing commands/command sequences during a write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. an er ase operation can erase one sector, multiple sectors, or the entire device. table 6.2 ? table 6.3 indicate the address space that ea ch sector occupi es. the device address space is divided into uniform 64kw/128kb sector s. a sector address is the set of address bits required to uniquely select a sector. i cc2 in ?dc characteristics? represents the active current specification for the write mode. ?ac characteristics? contains timing specification tables and timing diagrams for write operations. 7.9.1 ry/by# this feature allows the host system to detect when data is ready to be read by simply monitoring the ry/by# pin, which is a dedicated output and controlled by ce#. the device address space is divided into uniform 64 kw/128kb sectors. a sect or address is the set of address bits required to uniquely select a sector. 7.9.2 hardware reset the reset# input provides a hardware method of re setting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates an y operation in progress, tristates all outputs, resets the configuration register, and ig nores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. to ensure data integrity the operation that was interrupted should be rein itiated once the device is ready to accept another command sequence. when reset# is held at v ss , the device draws v cc reset current (i cc5 ). if reset# is held at v il , but not at v ss , the standby current is greater. reset# may be tied to the system reset circuitry which enables the system to read the boot- up firmware from the flash me mory upon a system reset. see figure 11.7 on page 53 and figure 11.8 on page 54 for timing diagrams. table 7.17 write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/ by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
36 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) note hardware reset operation during embedded erase is not recommended; permanent device damage may result. 7.9.3 software reset software reset is part of the command set (see table 12.1 on page 61 ) that also returns the device to array read mode and must be used for the following conditions: 1. to exit autoselect mode 2. when dq5 goes high during write status operation that indicates program or erase cycle was not successfully completed 3. exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if the device was previously in erase suspend mode. 5. after any aborted operations software functions and sample code note base = base address. the following is a c source code example of using the reset function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on span sion flash memory software development guidelines. /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; the following are additional points to consider when using the reset command: ? this command resets the sectors to the read and address bits are ignored. ? reset commands are ignored once erasure has begun until the operation is complete. ? once programming begins, the device ignores reset commands until the operation is complete ? the reset command may be written between the cycles in a program command sequence before programming begins (prior to the th ird cycle). this resets the sector to which the system was writing to the read mode. ? if the program command sequence is written to a sect or that is in the erase suspend mode, writing the reset command returns that sector to the erase-suspend-read mode. ? the reset command may be also written during an autoselect command sequence. ? if a sector has entered the autose lect mode while in the erase suspend mode, writing the reset command returns that sector to the erase-suspend-read mode. ? if dq1 goes high during a write buffer programming oper ation, the system must write the "write to buffer abort reset" command sequence to reset the device to reading array data. the standard reset command does not work during this condition. ? to exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see command table for details]. table 7.18 reset (lld function = lld_resetcmd) cycle operation byte address word address data reset command write base + xxxh base + xxxh 00f0h
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 37 data sheet (advance information) 8. advanced sector protection/unprotection the advanced sector protec tion/unprotection feature disables or ena bles programming or erase operations in any or all sectors and can be implemented thr ough software and/or hardware methods, which are independent of each other. this sectio n describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 8.1 . figure 8.1 advanced sector pr otection/unprotection hardware methods software methods wp#/acc = v il (highe s t or lowe s t s ector locked) p ass word method (dq2) per s i s tent method (dq1) lock regi s ter (one time progr a mm ab le) ppb lock bit 1,2, 3 64- b it p ass word (one time protect) 1 = ppb s unlocked 0 = ppb s locked memory arr a y s ector 0 s ector 1 s ector 2 s ector n-2 s ector n-1 s ector n 3 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n per s i s tent protection bit (ppb) 4,5 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dyn a mic protection bit (dyb) 6,7, 8 6. 0 = s ector protected, 1 = s ector unprotected. 7. protect effective only if ppb lock bit i s u nlocked a nd corre s ponding ppb i s ?1 ? ( u nprotected). 8 . vol a tile bit s : def au lt s to us er choice u pon power- u p ( s ee ordering option s ). 4. 0 = s ector protected, 1 = s ector unprotected. 5. ppb s progr a mmed individ ua lly, bu t cle a red collectively 1. bit i s vol a tile, a nd def au lt s to ? 1 ? on re s et. 2. progr a mming to ? 0 ? lock s a ll ppb s to their c u rrent s t a te. 3 . once progr a mmed to ? 0 ? , re qu ire s h a rdw a re re s et to u nlock. 3 . n = highe s t addre ss s ector.
38 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 8.1 lock register as shipped from the factory, all devices default to th e persistent mode when power is applied, and all sectors are unprotected, unless otherwise chos en through the dyb ordering option (see ordering information on page 5 ). the device programmer or host system must then choose which sector protection method to use. programming (setting to ?0?) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: ? lock register persistent protection mode lock bit (dq1) ? lock register password protection mode lock bit (dq2) for programming lock register bits refer to table 12.2 on page 63 and table 12.4 on page 65 . notes 1. if the password mode is chosen, the pass word must be programmed before setting the corresponding lock register bit. 2. after the lock register bits command set entry command sequence is written, reads and writes for sector 0 are disabled, while reads from other sectors are allowed until exiting this mode. 3. if both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 4. once the password mode lock bit is programmed, the persistent mode lock bit is permanently disabled, and no changes to the protection scheme are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. after selecting a sector protection method, each sect or can operate in any of the following three states: 1. constantly locked. the selected sectors are protecte d and can not be reprogrammed unless ppb lock bit is cleared via a password, hardware reset, or power cycle. 2. dynamically locked. the selected sectors are protect ed and can be altered via software commands. 3. unlocked. the sectors are unprotected and c an be erased and/or programmed. these states are controlled by the bit types described in section 8.2 ? section 8.5 . 8.2 persistent protection bits the persistent protection bits ar e unique and nonvolatile for each sector and have the same endurances as the flash memory. preprogramming and verification prio r to erasure are handled by the device, and therefore do not require system monitoring. notes 1. each ppb is individually programm ed and all are eras ed in parallel. 2. while programming ppb for a sector , array data can be read from an y other sector, except sector 0 (used for data# polling) and the sector in which sector ppb is being programmed. 3. entry command disables reads and writes for the sector selected. 4. reads within that sector return the ppb status for that sector. 5. all reads must be performed using the read mode. 6. the specific sector address (a25-a16 gl01g p, a24-a16 gl512p, a23-a16 gl256p, a22-a16 gl128p) are written at the same time as the program command. 7. if the ppb lock bit is set, the ppb program or erase command does not execute and times-out without programming or erasing the ppb. table 8.1 lock register dq15-3 dq2 dq1 dq0 don?t care password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 39 data sheet (advance information) 8. there are no means for individually erasing a s pecific ppb and no specific sector address is required for this operation. 9. exit command must be issued after the executi on which resets the device to read mode and re- enables reads and writes for sector 0. 10. the programming state of the ppb for a given sect or can be verified by writing a ppb status read command to the device as described by the flow chart shown in figure 8.2 . figure 8.2 ppb program/erase algorithm re a d byte twice addr = s a0 enter ppb comm a nd s et. addr = ba progr a m ppb bit. addr = s a dq5 = 1? ye s ye s ye s no no no ye s dq6 = toggle? dq6 = toggle? re a d byte. addr = s a pa ss fail i ssu e re s et comm a nd exit ppb comm a nd s et dq0 = '1' (er as e) '0' (pgm.)? re a d byte twice addr = s a0 no w a it 500 s
40 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 8.2.1 dynamic protection bits dynamic protection bits are volatile and unique for eac h sector and can be individually modified. dybs only control the protection scheme for unpr otected sectors that have their ppbs cl eared (erased to ?1?). by issuing the dyb set or clear command sequences, the dybs are set (programmed to ?0?) or cleared (erased to ?1?), thus placing each sector in the prot ected or unprotected state respective ly. this feature allows software to easily protect sectors against inadvertent changes ye t does not prevent the easy removal of protection when changes are needed. notes 1. the dybs can be set (programmed to ?0?) or cleared (erased to ?1?) as often as needed. when the parts are first shipped, the ppbs are cleared (erased to ?1?) and upon power up or reset, the dybs can be set or cleared depending upon the ordering option chosen. 2. if the option to clear the dybs after power up is chosen, (erased to ?1?), then the sectorsmay be modified depending upon the ppb state of that sector (see table 8.2 ). 3. the sectors would be in the protected state if t he option to set the dybs after power up is chosen (programmed to ?0?). 4. it is possible to have sectors that are persistent ly locked with sectors that are left in the dynamic state. 5. the dyb set or clear commands for the dynamic se ctors signify protected or unprotectedstate of the sectors respectively. however, if there is a ne ed to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit onc e again locks the ppbs, a nd the device operates normally again. 6. to achieve the best prot ection, it is recommended to execute the ppb lock bit set command early in the boot code and protect the boot code by holding wp#/acc = v il . note that the ppb and dyb bits have the same function when wp#/acc = v hh as they do when acc =v ih . 8.3 persistent protection bit lock bit the persistent protection bit lock bit is a global volat ile bit for all sectors. when set (programmed to ?0?), it locks all ppbs and when cleared (programmed to ?1?), allows the ppbs to be ch anged. there is only one ppb lock bit per device. notes 1. no software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. 2. the ppb lock bit must be se t (programmed to ?0?) only after all ppbs are configured to the desired settings. 8.4 password protection method the password protection method allows an even higher leve l of security than the pers istent sector protection mode by requiring a 64-bit password for unlocking the device ppb lock bit. in addition to this password requirement, after power up and reset, the ppb lock bi t is set ?0? to maintain the password mode of operation. successful execution of the password unlock command by entering the entire password clears the ppb lock bit, allowing for se ctor ppbs modifications. notes 1. there is no special addressing order required for programming the password. once the password is written and verified, the password mode locking bit must be set in order to prevent access. 2. the password program command is only capable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out with the cell as a ?0?. 3. the password is all ?1?s when shipped from the factory. 4. all 64-bit password combinations are valid as a password.
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 41 data sheet (advance information) 5. there is no means to verify what the password is after it is set. 6. the password mode lock bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 7. the password mode lock bit is not erasable. 8. the lower two address bits (a1?a0) are valid dur ing the password read, password program, and password unlock. 9. the exact password must be entered in order for the unlocking function to occur. 10. the password unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combin ations in an attempt to correctly match a password. 11. approximately 1 s is required for unlocking the devi ce after the valid 64-bit password is given to the device. 12. password verification is only allowed during the password programming operation. 13. all further commands to the password region are disabled and all operations are ignored. 14. if the password is lost after setting the password mode lock bit, there is no way to clear the ppb lock bit. 15. entry command sequence must be issued prior to any of any operation and it disables reads and writes for sector 0. reads and writes for ot her sectors excluding sector 0 are allowed. 16. if the user attempts to program or erase a pr otected sector, the device ignores the command and returns to read mode. 17. a program or erase command to a protected sector enables status polling and returns to read mode without having modified the c ontents of the protected sector. 18. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing individual status read commands dyb status, ppb status, and ppb lock status to the device.
42 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) figure 8.3 lock register program algorithm write unlock cycle s : addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h write enter lock regi s ter comm a nd: addre ss 555h, d a t a 40h progr a m lock regi s ter d a t a addre ss xxxh, d a t a a0h addre ss xxxh * , d a t a pd unlock cycle 1 unlock cycle 2 xxxh = addre ss don ? t c a re progr a m d a t a (pd): s ee text for lock regi s ter definition s c au tion: lock regi s ter c a n only b e prog a mmed once. w a it 4 m s (recommended) pa ss . write lock regi s ter exit comm a nd: addre ss xxxh, d a t a 90h addre ss xxxh, d a t a 00h device ret u rn s to re a ding a rr a y. perform polling algorithm ( s ee write oper a tion s t a t us flowch a rt) ye s ye s no no done? dq5 = 1? error condition (exceeded timing limit s ) fail. write re s t comm a nd to ret u rn to re a ding a rr a y.
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 43 data sheet (advance information) 8.5 advanced sector protection software examples table 8.2 contains all possibl e combinations of the dyb, ppb, and ppb lock bit relating to the status of the sector. in summary, if the ppb lock bit is locked (set to ?0?), no changes to the ppbs are allowed. the ppb lock bit can only be unlocked (reset to ?1?) through a hardware reset or power cycle. see also figure 8.1 for an overview of the advanced sector protection feature. 8.6 hardware data protection methods the device offers two main types of data protec tion at the sector level via hardware control: ? when wp#/acc is at v il , the either the highest or lowest se ctor is locked (device specific). there are additional methods by which intended or acci dental erasure of any se ctors can be prevented via hardware means. the following subs ections describes these methods: 8.6.1 wp#/acc method the write protect feature pr ovides a hardware method of protecting one outermost sector. this function is provided by the wp#/acc pin and overrides the prev iously discussed sector protection/unprotection method. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the highest or lowest sector independently of whether the sector was protected or un protected using the method described in "advanced sector pr otection/unprotection" section. if the system asserts v ih on the wp#/acc pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. that is, sector protecti on or unprotection for these sectors depends on whether they were last protected or unprotected. note that the wp#/acc pin must not be left floating or unconnected as inconsistent behavior of the device may result. the wp#/acc pin must be held stable during a command sequence execution. note if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is increased. see table 11.6 on page 50 for details. 8.6.2 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase ci rcuits are disabled, and the device resets to reading array data. subsequent wr ites are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . table 8.2 sector protection schemes: dyb, ppb and ppb lock bit combinations unique device ppb lock bit 0 = locked 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status any sector 0 0 x protected through ppb any sector 0 0 x protected through ppb any sector 0 1 1 unprotected any sector 0 1 0 protected through dyb any sector 1 0 x protected through ppb any sector 1 0 x protected through ppb any sector 1 1 0 protected through dyb any sector 1 1 1 unprotected
44 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 8.6.3 write pulse ?glitch protection? noise pulses of less than 5 ns (typical) on oe#, ce# or we # do not initiate a write cycle. 8.6.4 power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device d oes not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. 9. power conservation modes 9.1 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.3 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc4 in ?dc characteristics? r epresents the standby current specification 9.2 automatic sleep mode the automatic sleep mode minimizes flash device ener gy consumption. the devi ce automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals . standard address access timings pr ovide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc6 in section 11.6 represents the automatic slee p mode current specification. 9.3 hardware reset# input operation the reset# input provides a hardware method of re setting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates an y operation in progress, tristates all outputs, and ignores all read/write commands for th e duration of the reset# pulse. the device also resets the internal state machine to reading arra y data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at v ss 0.3 v, the device draws i cc reset current (i cc5 ). if reset# is held at v il but not within v ss 0.3 v, the standby current is greater. reset# may be tied to the system reset circuitry and thus, a system reset would also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. 9.4 output disable (oe#) when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state.
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 45 data sheet (advance information) 10. secured silicon sector flash memory region the secured silicon sector provides an extra flash memo ry region that enables permanent part identification through an electronic serial number (esn). the secu red silicon sector is 128 words in length and all secured silicon reads outside of the 128-word addr ess range returns invalid data. the secured silicon sector indicator bit, dq7, (at autose lect address 03h) is used to indicate whether or not the secured silicon sector is locked when sh ipped from the factory. please note the following general conditions: ? on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. ? reads outside of sector sa0 return memory array data. ? sector sa0 is remapped from memory array to secured silicon sector array. ? once the secured silicon sector entry command is issued, the secured silicon sector exit command must be issued to exit secured silicon sector mode. ? the secured silicon sector is not accessible when the device is executing an embedded program or embedded erase algorithm. ? the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. 10.1 factory locked secured siliconsector the secured silicon sector is alwa ys protected when shipped from the factory and has the secured silicon sector indicator bit (dq7) permanently set to a ?1?. this prevents cloning of a factory locked part and ensures the security of the esn and customer code once the product is shipped to the field. these devices are available pre-pr ogrammed with one of the following: ? a random, 8 word secure esn only within the secured silicon sector (at addresses 000000h - 000007h) ? both a random, secure esn and customer code through the spansion programming service. customers may opt to have their code programmed th rough the spansion programming services. spansion programs the customer's code, with or without t he random esn. the devices are then shipped from the spansion factory with the secured silicon sector perma nently locked. contact your local representative for details on using spansion programming services. 10.2 customer lockable secured silicon sector the secured silicon sector is typically shipped unprotected (dq7 set to ?0?), allowing customers to utilize that sector in any manner they choose. if the security feat ure is not required, the secured silicon sector can be treated as an additional flash memory space. please note the following: ? once the secured silicon sector area is protected, th e secured silicon sector i ndicator bit is permanently set to ?0.? ? the secured silicon sector can be read any number of times, but can be programmed and locked only once. the secured silicon sector lock must be used with caution as once locked, there is no procedure available for unlocking the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. ? the accelerated programming (acc) and unlock bypass functions are not available when the secured silicon sector is enabled. table 10.1 secured silicon sector addresses secured silicon sector address range customer lockable esn factory locked expressflash factory locked 000000h?000007h determined by customer esn esn or determined by customer 000008h?00007fh unavailable determined by customer
46 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) ? once the secured silicon sector is locked and verifi ed, the system must write the exit secured silicon sector region command sequence which return t he device to the memory array at sector 0. 10.3 secured silicon sector entry/exit command sequences the system can access the secured s ilicon sector region by issuing th e three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues the four-cycle exit secu red silicon sector command sequence. see command definition table [secured silicon sector command table, appendix table 12.1 on page 61 through table 12.4 on page 65 for address and data requirements for both command sequences. the secured silicon sector entry command allows the following commands to be executed ? read customer and factor y secured silicon areas ? program the customer secured silicon sector after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by sector sa0 within the memory array. this mode of operation continues unt il the system issues the exit secured silicon sector command sequence, or until power is removed from the device. software functions and sample code the following are c functions and source code examples of using the secured silicon sector entry, program, and exit commands. refer to the spansion low level driver user?s guide (available soon on www.spansion.com ) for general information on spansion flash memory software development guidelines. note base = base address. /* example: secsi sector entry command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0088; /* write secsi sector entry cmd */ note base = base address. /* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ table 10.2 secured silicon sector entry (lld function = lld_secsisectorentrycmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 555h base + 2aah 0055h entry cycle write base + aaah base + 555h 0088h table 10.3 secured silicon sector program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 555h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 47 data sheet (advance information) note base = base address. /* example: secsi sector exit command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0090; /* write secsi sector exit cycle 3 */ *( (uint16 *)base_addr + 0x000 ) = 0x0000; /* write secsi sector exit cycle 4 */ 11. electrical specifications 11.1 absolute maximum ratings notes 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions inputs or i/os may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 11.2 . 2. minimum dc input voltage on pins a9 and acc is -0.5v. during voltage transitions, a9 and acc may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 . maximum dc voltage on pins a9 and acc is +12.5 v, which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 11.1 maximum negative overshoot waveform table 10.4 secured silicon sector exit (lld function = lld_secsisectorexitcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 555h base + 2aah 0055h exit cycle 3 write base + aaah base + 555h 0090h exit cycle 4 write base + aaah base + 000h 0000h description rating storage temperature, plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground all inputs and i/os except as noted below (note 1) ?0.5 v to v cc + 0.5 v v cc (note 1) ?0.5 v to +4.0 v v io ?0.5v to +4.0v a9 and acc (note 2) ?0.5 v to +12.5 v output short circuit current (note 3) 200 ma 20 n s 20 n s +0 . 8 v ?0 .5 v 20 n s ?2 .0 v
48 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) figure 11.2 maximum positive overshoot waveform 11.2 operating ranges notes 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. see also ordering information on page 5 . 3. for valid v cc /v io range combinations, see ordering information on page 5 . the i/os do not operate at 3 v when v io = 1.8 v. 11.3 test conditions figure 11.3 test setup note diodes are in3064 or equivalent. 20 n s 20 n s 20 n s v cc +2.0 v +2.0 v v cc +0.5 v specifications range ambient temperature (ta), industrial (i) device ?40c to +85c supply voltages v cc +2.7 v to 3.6 v or +3.0 v to 3.6 v v io supply voltages v io +1.65 v to v cc 2.7 k c l 6.2 k 3.3 v device under te s t
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 49 data sheet (advance information) note if v io < v cc , the reference level is 0.5 v io . 11.4 key to switching waveforms 11.5 switching waveforms figure 11.4 input waveforms and measurement levels note if v io < v cc , the input measurement reference level is 0.5 v io . table 11.1 test specifications test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?v io v input timing measurement reference levels (see note) 0.5v io v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v io 0.0 v 0.5 v io 0.5 v io v output measurement level input
50 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 11.6 dc characteristics notes 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. i cc active while embedded erase or embedded program or write buffer programming is in progress. 3. not 100% tested. 4. automatic sleep mode enables the lower power mode when addresses remain stable tor t acc + 30 ns. 5. v io = 1.65?3.6 v 6. v cc = 3 v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at 3v. table 11.2 s29gl-p dc characterist ics (cmos compatible) parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc v cc = v cc max wp/acc 2.0 a others 1.0 i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (1) ce# = v il , oe# = v ih , v cc = v ccmax , f = 1 mhz 6 20 ma ce# = v il , oe# = v ih , v cc = v ccmax , f = 5 mhz 30 50 ce# = v il , oe# = v ih , v cc = v ccmax , f = 10 mhz 60 100 i io2 v io non-active output ce# = v il, oe# = v ih 0.2 10 ma i cc2 v cc intra-page read current (1) ce# = v il, oe# = v ih, v cc = v ccmax , f = 10 mhz 1 10 ma ce# = v il , oe# = v ih , v cc = v ccmax , f = 33 mhz 5 20 i cc3 v cc active erase/ program current ( 2 , 3 ) ce# = v il, oe# = v ih, v cc = v ccmax 50 90 ma i cc4 v cc standby current ce#, reset# = v cc 0.3 v, oe# = v ih, v cc = v ccmax v il = v ss + 0.3 v/-0.1v, 15 a i cc5 v cc reset current v cc = v ccmax; v il = v ss + 0.3 v/-0.1v, reset# = v ss 0.3 v 250 500 a i cc6 automatic sleep mode (4) v cc = v ccmax , v ih = v cc 0.3 v, v il = v ss + 0.3 v/-0.1v, wp#/acc = v ih 15 a i acc acc accelerated program current ce# = v il, oe# = v ih, v cc = v ccmax, wp#/acc = v hh wp#/acc pin 10 20 ma v cc pin 50 80 v il input low voltage (5) ?0.1 0.3 x v io v v ih input high voltage (5) 0.7 x v io v io + 0.3 v v hh voltage for program acceleration v cc = 2.7 ?3.6 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.5 v v ol output low voltage (5) i ol = 100 a 0.15 x v io v v oh output high voltage (5) i oh = -100 a 0.85 x v io v v lko low v cc lock-out voltage (3) 2.3 2.5 v
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 51 data sheet (advance information) 11.7 ac characteristics 11.7.1 s29gl-p read- only operations notes 1. ce#, oe# = v il 2. oe# = v il 3. not 100% tested. 4. see figure 11.3 and table 11.1 for test specifications. 5. unless otherwise indicated, ac specifications for 110 ns speed options are tested with v io = v cc = 2.7 v. ac specifications fo r 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. figure 11.5 read operation timings table 11.3 s29gl-p read-only operations parameter description (notes) test setup speed options jedec std. 110 110 120 130 unit t avav t rc read cycle time v io = v cc = 2.7 v min 110 120 ns v io = 1.65 v to v cc , v cc = 3 v 110 130 t avqv t acc address to output delay (1) v io = v cc = 2.7 v max 110 120 ns v io = 1.65 v to v cc , v cc = 3 v 110 130 ns t elqv t ce chip enable to output delay (2) v io = v cc = 2.7 v max 110 120 ns v io = 1.65 v to v cc , v cc = 3 v 110 130 ns t pac c page access time max 25 25 25 25 ns t glqv t oe output enable to output delay max 25 30 25 30 ns t ehqz t df chip enable to output high z (3) max 20 ns t ghqz t df output enable to output high z (3) max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (3) read min 0 ns toggle and data# polling min 10 ns t ceh chip enable hold time read min 35 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df t ceh
52 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) figure 11.6 page read timings note figure 11.6 shows word mode. addresses are a2:a-1 for byte mode. 11.7.2 hardware reset (reset#) am a x : a2 ce# oe# a2 : a0 d a t a b us sa me p a ge a a a b ac ad q a q b qc qd t acc t pac c t pac c t pac c (see note) table 11.4 hardware reset (reset#) parameter description speed unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode or write mode min 35 s t ready reset# pin low (not during embedded algorithms) to read mode or write mode min 35 s t rp reset# pulse width min 35 s t rh reset high time before read min 200 ns t rpd reset# low to standby mode min 10 s t rb ry/by# recovery time min 0 ns
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 53 data sheet (advance information) figure 11.7 reset timings note ce#, oe# and we# must be at logic high during reset time. notes 1. v io < v cc + 200 mv. 2. v io and v cc ramp must be synchornized during power up. 3. if reset# is not stable for t vcs or t vios : the device does not permit any read and write operations. a valid read operation returns ffh. a hardware reset is required. 4. v cc maximum power-up current (rst=v il ) is 20 ma. table 11.5 power-up sequence timings parameter description speed unit t vcs reset low time from rising edge of v cc (or last reset pulse) to rising edge of reset# min 35 s t vios reset low time from rising edge of v io (or last reset pulse) to rising edge of reset# min 35 s t rh reset high time before read max 200 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
54 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) figure 11.8 power-up sequence timings 11.7.3 s29gl-p erase and program operations notes 1. not 100% tested. 2. see section 11.6 for more information. 3. for 1?32 words/1?64 bytes programmed. 4. effective write buffer specification is based upon a 32-word/64-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 110 ns speed option are tested with v io = v cc = 2.7 v. ac specifications for 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. 6. write cycle time = access time at v cc . v cc min v cc v io min v io ce# reset# t rh t vios t vcs table 11.6 s29gl-p erase and program operations parameter description unit speed options unit jedec std. 110 120 130 t avav t wc write cycle time (note 1) min 110 (note 6) 120 130 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe # high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2 , 3 ) typ 480 s effective write buffer program operation (notes 2 , 4 )per word typ 15 s accelerated effective write buffer program operation (notes 2 , 4 ) per word typ 13.5 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) ty p 0 . 5 s e c t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 35 s t busy erase/program valid to ry/by# delay max 90 ns t sea command cycle timout max 50 s
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 55 data sheet (advance information) figure 11.9 program operation timings notes 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows de vice in word mode. figure 11.10 accelerated progra m timing diagram notes 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 11.3 and table 11.1 for test specifications. oe# we# ce# v cc d a t a addre ss e s t d s t ah t dh t wp pd t whwh1 t wc t a s t wph t vc s 555h pa pa re a d s t a t us d a t a (l as t two cycle s ) a0h t c s s t a t us d out progr a m comm a nd s e qu ence (l as t two cycle s ) ry/by# t rb t bu s y t ch pa acc t vhh v hh v il or v ih v il or v ih t vhh
56 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) figure 11.11 chip/sector erase operation timings notes 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status.? 2. these waveforms are for the word mode figure 11.12 data# polling timings (during embedded algorithms) notes 1. va = valid address. illustration shows first status cycle a fter command sequence, last status read cycle, and array data read cycle. 2. t oe for data polling is 45 ns when v io = 1.65 to 2.7 v and is 35 ns when v io = 2.7 to 3.6 v oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy we# ce# oe# high z t oe high z dq7 dq6?q0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 57 data sheet (advance information) figure 11.13 toggle bit timings (during embedded algorithms) note a = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cyc le, and array data read cycle figure 11.14 dq2 vs. dq6 note dq2 toggles only when read at an address within an erase-suspended sector. the system can use oe# or ce# to toggle dq2 and dq6. oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq2 and dq6 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
58 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 11.7.4 s29gl-p alternate ce# cont rolled erase and program operations notes 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?32 words/1?64 bytes programmed. 4. effective write buffer specification is based upon a 32-word/64-byte write buffer operation. 5. unless otherwise indicated, ac specifications are tested with v io = 1.8 v and v cc = 3.0 v 6. write cycle time = access time at v cc . table 11.7 s29gl-p alternate ce# contro lled erase and program operations parameter description (notes) speed options jedec std. 110 120 130 unit t avav t wc write cycle time (note 1) min 110 (note 6) 120 130 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t elax t ah address hold time min 45 ns t aht address hold time from ce# or oe # high during toggle bit polling min 0 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2 , 3 ) typ 480 s effective write buffer program operation (notes 2 , 4 ) per word ty p 1 5 s effective accelerated write buffer program operation (notes 2 , 4 ) per word typ 13.5 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) ty p 0 . 5 s e c
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 59 data sheet (advance information) figure 11.15 alternate ce# controlled write (erase/program) operation timings notes 1. figure 11.15 indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy
60 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 11.7.5 erase and programming performance notes 1. typical program and erase times assume the following conditions: 25c, 3.6 v v cc , 10,000 cycles, checkerboard pattern. 2. under worst case conditions of -40c, v cc = 3.0 v, 100,000 cycles. 3. effective write buffer specification is based upon a 32-word write buffer operation. 4. the typical chip programming time is considerably less than the maximum chip programming time listed, since most words progra m faster than the maximum program times listed. 5. in the pre-programming step of the embedded erase algo rithm, all bits are programmed to 00h before erasure. 6. system-level overhead is the time required to execute th e two- or four-bus-cycle sequence for the program command. see tables 12.1 ? 12.4 . 11.7.6 tsop pin and bg a package capacitance notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. table 11.8 erase and programming performance parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 3.5 sec excludes 00h programming prior to erasure (note 5) chip erase time s29gl128p 64 256 sec s29gl256p 128 512 s29gl512p 256 1024 s29gl01gp 512 2048 total write buffer time (note 3) 480 s excludes system level overhead (note 6) total accelerated write buffer programming time (note 3) 432 s chip program time (note 4) s29gl128p 123 sec s29gl256p 246 s29gl512p 492 s29gl01gp 984 table 1: parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf bga 3.9 4.7 pf
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 61 data sheet (advance information) 12. appendix this section contains information relating to softwar e control or interfacing with the flash device. for additional information and assistance regarding software, see section 5. for the latest information, explore the spansion web site at www.spansion.com . 12.1 command definitions writing specific address and data co mmands or sequences into the co mmand register initiates device operations. tables 12.1 ? 12.4 define the valid register command sequences. writing incorrect address and data values or writing them in the improper se quence can place the device in an unknown state. a reset command is then required to return the device to reading array data. legend x = don?t care ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever ha ppens later. pd = data to be programmed at location pa. data latches on the rising edge of the we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a max ?a16 uniquely select any sector. wbl = write buffer location. the address must be within the same write buffer page as pa. wc = word count is the number of write buffer locations to load minus 1. notes 1. see table 7.1 on page 14 for description of bus operations. 2. all values are in hexadecimal. 3. all bus cycles are write cycles unless otherwise noted. 4. data bits dq15-dq8 are don?t cares for unlock and command cycles. 5. address bits a max :a16 are don?t cares for unlock and command cycles, unless sa or pa required. (a max is the highest address pin.). 6. no unlock or command cycles required when reading array data. table 12.1 s29gl-p memory array command definitions, x16 command (notes) cycles bus cycles (notes 1 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (6) 1ra rd reset (7) 1 xxx f0 autoselect ( 8 , 9 ) manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id (8) 4 555 aa 2aa 55 555 90 x01 227e x0e (8) x0f (8) sector protect verify (10) 4 555 aa 2aa 55 555 90 [sa]x02 (10) secure device verify (11) 4 555 aa 2aa 55 555 90 x03 (11) cfi query (12) 155 98 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 3 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1 sa 29 write-to-buffer-abort reset (13) 3 555 aa 2aa 55 555 f0 unlock bypass enter 3 555 aa 2aa 55 555 20 program (14) 2 xxx a0 pa pd sector erase (14) 2 xxx 80 sa 30 chip erase (14) 2 xxx 80 xxx 10 reset (15) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend/program suspend (16) 1 xxx b0 erase resume/program resume (17) 1 xxx 30 secured silicon sector entry 3 555 aa 2aa 55 555 88 secured silicon sector exit (18) 4 555 aa 2aa 55 555 90 xx 00
62 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 7. the reset command is required to return to reading array data w hen device is in the autoselect mode, or if dq5 goes high (whi le the device is providing status data). 8. see table 7.2 on page 17 for device id values and definitions. 9. the fourth, fifth, and sixth cycles of the autoselect command sequence are read cycles. 10. the data is 00h for an unprotected sector and 01h for a pr otected sector. see ?autoselect command sequence? for more informa tion. this is same as ppb status read except that the protect and unprotect statuses are inverted here. 11. the data value for dq7 is ?1? for a serialized, protected secured silicon sector region and ?0? for an unserialized, unprote cted region. see table 7.3 on page 17 for data and definitions. 12. command is valid when device is ready to read array data or when device is in autoselect mode. 13. command sequence returns device to reading array after being placed in a write-to-buffer-abort state. full command sequence is required if resetting out of abort while in unlock bypass mode. 14. the unlock-bypass command is required prior to the unlock-bypass-program command. 15. the unlock-bypass-reset command is required to return to read ing array data when the device is in the unlock bypass mode. 16. the system can read and program/program suspend in non-erasin g sectors, or enter the autoselect mode, when in the erase susp end mode. the erase suspend command is valid only during a sector erase operation. 17. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 18. the exit command returns the device to reading the array.
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 63 data sheet (advance information) legend x = don?t care rd(0) = read data. sa = sector address. address bits a max ?a16 uniquely select any sector. pwd = password pwd x = password word0, word1, word2, and word3. data = lock register contents: pd(0) = secured silicon sector pr otection bit, pd(1) = persistent protection mode lock bit, pd(2 ) = password protection mode lock bit. notes 1. see table 7.1 on page 14 for description of bus operations. 2. all values are in hexadecimal. 3. all bus cycles are write cycles unless otherwise noted. 4. data bits dq15-dq8 are don?t cares for unlock and command cycles. 5. address bits a max :a16 are don?t cares for unlock and command cycles, unless sa or pa required. (a max is the highest address pin.) 6. all lock register bits are one-time programmable. program state = ?0? and the erase state = ?1.? the persistent protection mo de lock bit and the password protection mode lock bit cannot be programmed at the same time or the lock register bits program operation aborts and returns t he device to read mode. lock register bits that are reserved for future use default to ?1?s.? the lock register is shipped out as ?ffff?s? before lock regis ter bit program execution. 7. the exit command returns the device to reading the array. 8. if any command set entry command was written, an exit command must be issued to reset the device into read mode. 9. for pwdx, only one portion of the password can be programmed per each ?a0? command. 10. note that the password portion can be entered or read in any or der as long as the entire 64-bit password is entered or read. 11. if acc = v hh , sector protection matches when acc = v ih . 12. protected state = ?00h,? unprotected state = ?01h.? 13. the all ppb erase command embeds programming of all ppb bits before erasure. table 12.2 s29gl-p sector protection command definitions, x16 command (notes) cycles bus cycles (notes 1 ? 5 ) first/seventh second third fourth fifth sixth addr data addr data addr data addr data addr data addr data lock register command set entry 3 555 aa 2aa 55 555 40 program (6) 2 xxx a0 xxx data read (6) 177hdata command set exit ( 7 , 8 ) 2 xxx 90 xxx 00 password protection command set entry 3 555 aa 2aa 55 555 60 password program (9) 2 xxx a0 pwa x pwd x password read (10) 4 00 pwd0 01 pwd 1 02 pwd 2 03 pwd 3 password unlock (10) 7 00 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 00 29 command set exit ( 7 , 8 ) 2 xxx 90 xxx 00 global non-volatile ppb command set entry 3 555 aa 2aa 55 555 c0 ppb program ( 11 , 12 ) 2 xxx a0 sa 00 all ppb erase (13) 2 xxx 80 00 30 ppb status read (12) 1 sa rd (0) ppb command set exit ( 7 , 8 ) 2 xxx 90 xxx 00 global non- volatile freeze ppb lock command set entry 3 555 aa 2aa 55 555 50 ppb lock set (12) 2 xxx a0 xxx 00 ppb lock status read (12) 1 xxx rd (0) ppb lock command set exit ( 7 , 8 ) 2 xxx 90 xxx 00 volatile dyb command set entry 3 555 aa 2aa 55 555 e0 dyb set ( 11 , 12 ) 2 xxx a0 sa 00 dyb clear (12) 2 xxx a0 sa 01 dyb status read (12) 1 sa rd (0) dyb command set exit ( 7 , 8 ) 2 xxx 90 xxx 00
64 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) legend x = don?t care ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever ha ppens later. pd = data to be programmed at location pa. data latches on the rising edge of the we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a max ?a16 uniquely select any sector. wbl = write buffer location. the address must be within the same write buffer page as pa. wc = word count is the number of write buffer locations to load minus 1. notes 1. see table 7.1 on page 14 for description of bus operations. 2. all values are in hexadecimal. 3. all bus cycles are write cycles unless otherwise noted. 4. data bits dq15-dq8 are don?t cares for unlock and command cycles. 5. address bits a max :a16 are don?t cares for unlock and command cycles, unless sa or pa required. (a max is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data w hen device is in the autoselect mode, or if dq5 goes high (whi le the device is providing status data). 8. see table 7.2 on page 17 for device id values and definitions. 9. the fourth, fifth, and sixth cycles of the autoselect command sequence are read cycles. 10. the data is 00h for an unprotected sector and 01h for a pr otected sector. see ?autoselect command sequence? for more informa tion. this is same as ppb status read except that the protect and unprotect statuses are inverted here. 11. the data value for dq7 is ?1? for a serialized, protected secured silicon sector region and ?0? for an unserialized, unprote cted region. see table 7.3 on page 17 for data and definitions. 12. command is valid when device is ready to read array data or when device is in autoselect mode. 13. command sequence returns device to reading array after being placed in a write-to-buffer-abort state. full command sequence is required if resetting out of abort while in unlock bypass mode. 14. the unlock-bypass command is required prior to the unlock-bypass-program command. 15. the unlock-bypass-reset command is required to return to read ing array data when the device is in the unlock bypass mode. 16. the system can read and program/program suspend in non-erasin g sectors, or enter the autoselect mode, when in the erase susp end mode. the erase suspend command is valid only during a sector erase operation. 17. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 18. the exit command returns the device to reading the array. table 12.3 s29gl-p memory array command definitions, x8 command (notes) cycles bus cycles (notes 1 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (6) 1ra rd reset (7) 1 xxx f0 autoselect ( 8 , 9 ) manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id (8) 4 aaa aa 555 55 aaa 90 x02 xx7e x1c (8) x1e (8) sector protect verify (10) 4 aaa aa 555 55 aaa 90 [sa]x04 (10) secure device verify (11) 4 aaa aa 555 55 aaa 90 x06 (11) cfi query (12) 1aa 98 program 4 aaa aa 555 55 aaa a0 pa pd write to buffer 3 aaa aa 555 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1 sa 29 write-to-buffer-abort reset (13) 3 aaa aa 555 55 555 f0 unlock bypass enter 3 aaa aa 555 55 aaa 20 program (14) 2 xxx a0 pa pd sector erase (14) 2 xxx 80 sa 30 chip erase (14) 2 xxx 80 xxx 10 reset (15) 2 xxx 90 xxx 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend/program suspend (16) 1 xxx b0 erase resume/program resume (17) 1 xxx 30 secured silicon sector entry 3 aaa aa 555 55 aaa 88 secured silicon sector exit (18) 4 aaa aa 555 55 aaa 90 xx 00
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 65 data sheet (advance information) legend x = don?t care rd(0) = read data. sa = sector address. address bits a max ?a16 uniquely select any sector. pwd = password pwd x = password word0, word1, word2, and word3. data = lock register contents: pd(0) = secured silicon sector pr otection bit, pd(1) = persistent protection mode lock bit, pd(2 ) = password protection mode lock bit. notes 1. see table 7.1 on page 14 for description of bus operations. 2. all values are in hexadecimal. 3. all bus cycles are write cycles unless otherwise noted. 4. data bits dq15-dq8 are don?t cares for unlock and command cycles. 5. address bits a max :a16 are don?t cares for unlock and command cycles, unless sa or pa required. (a max is the highest address pin.) 6. all lock register bits are one-time programmable. program state = ?0? and the erase state = ?1.? the persistent protection mo de lock bit and the password protection mode lock bit cannot be programmed at the same time or the lock register bits program operation aborts and returns t he device to read mode. lock register bits that are reserved for future use default to ?1?s.? the lock register is shipped out as ?ffff?s? before lock regis ter bit program execution. 7. the exit command returns the device to reading the array. 8. if any command set entry command was written, an exit command must be issued to reset the device into read mode. 9. for pwdx, only one portion of the password can be programmed per each ?a0? command. 10. note that the password portion can be entered or read in any or der as long as the entire 64-bit password is entered or read. 11. if acc = v hh , sector protection matches when acc = v ih . 12. protected state = ?00h,? unprotected state = ?01h.? 13. the all ppb erase command embeds programming of all ppb bits before erasure. table 12.4 s29gl-p sector protection command definitions, x8 command (notes) cycles bus cycles (notes 1 ? 5 ) first/seventh second/eighth third fourth fifth sixth addr data addr data addr data addr data addr data addr data lock register command set entry 3 aaa aa 555 55 aaa 40 bits program (6) 2 xxx a0 xxx data read (6) 100data command set exit ( 7 , 8 ) 2 xxx 90 xxx 00 password protection command set entry 3 aaa aa 555 55 aaa 60 password program (9) 2 xxx a0 pwa x pwd x password read (10) 8 00 pwd0 01 pwd 1 02 pwd 2 03 pwd 3 04 pwd 4 05 pwd 5 06 pwd 6 07 pwd 7 password unlock (10) 11 00 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 04 pwd 4 05 pwd 5 06 pwd 6 07 pwd 7 00 29 command set exit ( 7 , 8 ) 2 xxx 90 xxx 00 global non-volatile ppb command set entry 3 aaa aa 55 55 aaa c0 ppb program ( 11 , 12 ) 2 xxx a0 sa 00 all ppb erase (13) 2 xxx 80 00 30 ppb status read (12) 1 sa rd(0) ppb command set exit ( 7 , 8 ) 2 xxx 90 xxx 00 global non- volatile freeze ppb lock command set entry 3 aaa aa 555 55 aaa 50 ppb lock bit set (12) 2 xxx a0 xxx 00 ppb lock status read (12) 1 xxx rd(0) ppb lock command set exit ( 7 , 8 ) 2 xxx 90 xxx 00 volatile dyb command set entry 3 aaa aa 555 55 aaa e0 dyb set ( 11 , 12 ) 2 xxx a0 sa 00 dyb clear (12) 2 xxx a0 sa 01 dyb status read (12) 1 sa rd(0) dyb command set exit ( 7 , 8 ) 2 xxx 90 xxx 00
66 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) 12.2 common flash memory interface the common flash in terface (cfi) specification outlines device and host system software in terrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-in dependent, jedec id-independent, and forward- and back- ward-compatible for the specified flash device fam ilies. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h any time the device is ready to read array data . the system can read cfi infomation at the addresses given in tables 12.6?12.8 ). all reads outside of the cfi address ra nge, returns non-valid data. reads from other sectors are allowed, writes ar e not. to terminate re ading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 12.6?12.8 . the system must write the reset command to return the device to reading array data. the following is a c source code example of using the cfi entry and exit f unctions. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: cfi entry command */ *( (uint16 *)base_addr + 0x55 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ for further information, pl ease refer to the cfi specification (s ee jedec publications jep137-a and jesd68.01and cfi publication 100). please contact yo ur sales office for copi es of these documents. table 12.5 cfi query identification string addresses (x16) addresses (x8) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists)
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 67 data sheet (advance information) table 12.6 system interface string addresses (x16) addresses (x8) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 mv 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 mv 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0006h typical timeout per single byte/word write 2 n s 20h 40h 0006h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 0009h typical timeout per individual block erase 2 n ms 22h 44h 0013h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0003h max. timeout for byte/word write 2 n times typical 24h 48h 0005h max. timeout for buffer write 2 n times typical 25h 4ah 0003h max. timeout per individual block erase 2 n times typical 26h 4ch 0002h max. timeout for full chip erase 2 n times typical (00h = not supported) table 12.7 device geometry definition addresses (x16) addresses (x8) data description 27h 4eh 001bh 001ah 0019h 0018h device size = 2 n byte 1b = 1 gb, 1a= 512 mb, 19 = 256 mb, 18 = 128 mb 28h 29h 50h 52h 0002h 0000h flash device interface descripti on (refer to cfi publication 100) 2ah 2bh 54h 56h 0006h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0001h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 00xxh 000xh 0000h 000xh erase block region 1 information (refer to the cfi specification or cfi publication 100) 00ffh, 0003h, 0000h, 0002h =1 gb 00ffh, 0001h, 0000h, 0002h = 512 mb 00ffh, 0000h, 0000h, 0002h = 256 mb 007fh, 0000h, 0000h, 0002h = 128 mb 31h 32h 33h 34h 60h 64h 66h 68h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
68 s29gl-p mirrorbit tm flash family s29gl-p_00_a3 november 21, 2006 data sheet (advance information) table 12.8 primary vendor-specific extended query addresses (x16) addresses (x8) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 0014h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7- 2) 0101b = 90 nm mirrorbit 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0008h sector protect/unprotect scheme 0008h = advanced sector protection 4ah 94h 0000h simultaneous operation 00 = not supported, x = number of sectors 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 00xxh wp# protection 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h a0h 0001h program suspend 00h = not supported, 01h = supported
november 21, 2006 s29gl-p_00_a3 s29gl-p mirrorbit tm flash family 69 data sheet (advance information) 13. revision summary colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004?2006 spansion inc. all rights reserved. spansion, the spansion logo, mirrorbit, o rnand, hd-sim, and combinatio ns thereof are trademarks of spansion inc. other names are for informational purposes only and may be trademarks of their respecti ve owners. section description revision a0 (october 29, 2004) initial release. revision a1 (october 20, 2005) global revised all sections of document. revision a2 (october 19, 2006) global revised all sections of document. reformatted document to new template. changed speed options for s29gl01gp. revision a3 (november 21, 2006) ac characteristics erase and program operations table: changed t busy to a maximum specification.

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